Overview

On behalf of our client we are looking for a Digital ASIC/ FPGA Verification Engineer

Digital ASIC/FPGA verification as follows:

Mandatory:

• Ability to travel to Kista, Stockholm once per month

• Excellent skills in SystemVerilog/UVM

• Good programming skills (neat, commented, maintainable code, no warnings). Quality conscious!

• Excellent debugging skills with complex designs

• Experience with IP level and system level verification

• Proficient in verification planning, reporting and driving verification closure. Must understand how a verification project works, from start to finish

• Must be able to work both in team and independently

• Good communication skills, both written and oral English

• Good skills in working with UNIX and/or Linux

• At least 7 years in ASIC/FPGA industry

Meritorious:

• Experience with Matlab, and signal processing

• Experience with analog-mixed-signal type ASICs

• Experience in Specman/e with a few years of SystemVerilog/UVM is also suitable

• Experience using formal properties and tools, such as Jasper, OneSpin, InFact and similar

• Experience in using golden models/reference models in a test bench

• C-programming

• Experience in agile ways of working, in particular agile scrum

• Clearcase version control system experience

• VHDL knowledge

• Scripting in Perl, Python, Bash or C-shell

• More than 10 years in the ASIC/FPGA industry

If you would have such a candidate please ask him/her to self asses (none, novice, medium, senior, expert) for the following:

System Verilog:

UVM:

IP verification know-how:

Perl:

Python:

UNIX:

RTL+UPF simulations:

Clearcase:

UVM verification:

VHDL:

Start: Start date summer 2018, preferably June 1st or July 1st.

Duration: 6-12 months with likelihood for additional assignments/projects

Location: Lund

Work load: 100 %

Working language: English

Please, apply directly through our system with

– your updated CV

– your hourly rate (all included)

– name and telephone number to 2 reference persons eWork can contact (we will contact your reference persons first after contact with you)

– information on when you are available to start

– in the Motivation describe why you are suitable for this assignment – refer to earlier assignments, employments, education and personal qualities.

Tagged as: VHDL/FPGA/ASIC, System Verilog, HW verification

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