For our client we are looking for a

Job description:

The job is as IP designer with a secondary competence profile as IP verifier within our client´s digital ASIC projects.

The work includes:

• Design planning

• Design specification

• Design implementation

• Design documentation

• Design verification (regression + development verification)

• Miscellaneous tasks in connection to the block design

• Verification planning

• Verification specification

• Verification environment (creation/adaptation/maintenance).

• Verification documentation

• Test case creation

• Usage of uVC´s

• Usage of reference models (if needed)

• Constrained random testing

• Creation of Coverage matrix

• Etc.

A successful candidate is an experienced design & verification engineer with 5 or more years’ experience from both IP design and IP verification. Verification is done using System Verilog/UVM and constrained random methodology but also dedicated test-vectors and assertions are used.

Both written and spoken English skills are required. Personal profile should also include a positive attititude, a desire to assist fellow engineers, structured way of working, care with details and a natural talent in communicating with others.

You enjoy working both independently and in a small diverse team and you are focused on reaching result on time. As a person you must be thorough and able to work with many different people. The work will be carried out in a cross functional team using Agile ways of working.

Required skills:

• Education level: Master of Science or similar

• Excellent programming skills (VHDL, SV).

• Experienced in Hardware design/systemization.

• Experienced in HW design methodology.

• Experienced in WCDMA, GSM and/or LTE systems.

• Experience in using the System Verilog/UVM tools and methodology.

• Experience in system level verification is a plus.

• Knowledge of verification methodology in general.

• Knowledge in programming C, C++ and System C.

• Knowledge about Formal verification is a plus.

• Knowledge of SW design for an embedded environment.

• Good scripting skills using e.g. Python, TCL and/or Perl.

• Synthesis.

• Spyglass.

• Equivalence check.

• Knowledge about Agile ways of working is a plus.

Start: ASAP

Duration: End by 2019-05-31, with the option to extend. The contract will cover 6 months at the time.

Location: Lund

Work load: 100 %

Working language: English

Please, apply directly through our system with

– your updated CV

– your hourly rate (all included)

– name and telephone number to 2 reference persons eWork can contact (we will contact your reference persons first after contact with you)

– information on when you are available to start

– in the Motivation describe why you are suitable for this assignment – refer to earlier assignments, employments, education and personal qualities.

Tagged as: HW Design, HW verification

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