Overview
On behalf of our client we are looking for an IP design verification Engineer
Job description:
The job involves IP design verification within our client´s digital ASIC & FPGA projects.
The work includes:
• Verification planning
• Verification specification
• Verification environment (creation/adaptation/maintenance).
• Verification documentation
• Test case creation
• Usage of uVC´s
• Usage of reference models (if needed)
• Constrained random testing
• Creation of Coverage matrix
• Design documentation
• Design verification (regression + development verification)
• Miscellaneous tasks in connection to the block design
• Etc.
Most of the verification uses constrained random methodology but also dedicated test-vectors and assertions are used. A successful candidate is an experienced verification engineer with 5 or more years of IP verification experience. Verification shall be done using System Verilog/UVM.
Both written and spoken English skills are required. Personal profile should also include a positive attitude, a desire to assist fellow engineers, structured way of working, care with details and a natural talent in communicating with others.
You enjoy working both independently and in a small diverse team and you are focused on reaching result on time. As a person you must be thorough and able to work with many different people. The work will be carried out in a cross functional team using Agile ways of working.
Required skills:
• Education level: Master of Science or similar
• Experience in using the System Verilog/UVM tools and methodology.
• Experience of verification methodology in general.
• Excellent programming skills (SV, VHDL).
• Experience of SW design for an embedded environment.
• Experience in system level verification is a plus.
• Knowledge in Hardware design/systemization.
• Knowledge in HW design methodology.
• Knowledge in WCDMA, GSM and/or LTE systems.
• Knowledge in programming C, C++ and System C.
• Knowledge about Formal verification is a plus.
• Good scripting skills using e.g. Python, TCL and/or Perl.
• Knowledge of reference model development.
• Knowledge about Agile ways of working is a plus.
Start: ASAP
Duration: End by 2019-05-31, with the option to extend. The contract will cover 6 months at the time.
Location: Lund
Work load: 100 %
Working language: English
Please, apply directly through our system with
– your updated CV
– your hourly rate (all included)
– name and telephone number to 2 reference persons eWork can contact (we will contact your reference persons first after contact with you)
– information on when you are available to start
– in the Motivation describe why you are suitable for this assignment – refer to earlier assignments, employments, education and personal qualities.